High-level system description methodologies can allow designers and system architects to modify the traditional system design approach. Some languages, such as SystemC, may allow system architects to model a circuit or system at a transaction-level in order to test the specified functionality and get early performance reports.
SystemC is a set of library routines and macros implemented in C++, which makes it possible to simulate concurrent processes, each described by C++ syntax. Software objects instantiated in the SystemC framework may communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined.
The traditional design cycle for an integrated circuit still follows or often runs concurrently with this architectural modeling. The design will be written in a hardware description level usually at RTL (register transfer level) to be synthesized and finalized into silicon.
Some prior approaches are not able to quickly and efficiently monitor and analyze a circuit or system performance early in the design cycle resulting in a longer design cycle and slower time to market for the design.